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Some of the questions aren't working properly with the "Grade answers" feature. This is a known issue that will be addressed eventually.

Which of the following instructions is a J-format instruction?
- (A) jal
- (B) jr
- (C) bne
- (D) slt
- ANSWER: (A). jr and slt are R-format, and bne is I-format.
Which of the following instructions or pseudoinstructions does not involve an immediate value?
- (A) la
- (B) j
- (C) sw
- (D) jr
- ANSWER: (D). la and j use immediate addresses, and sw uses an immediate offset.
Which of the following instruction-format pairings is incorrect?
- (A) j - J-format
- (B) lb - R-format
- (C) slt - R-format
- (D) addi - I-format
- ANSWER: (B). lb is I-format (you need to specify an immediate as the offset).
Bits 6-10 of an R-format instruction are only used for particular instructions. Which of the following R-format instructions uses those bits?
- (A) sub
- (B) sll
- (C) mfhi
- (D) xor
- ANSWER: (B). Bits 6-10 are the "shift amount", or shamt. They are used for sll, srl, and sra, which is essentially the same as srl except in the sense that it works "as expected" for negative numbers.
I-format and J-format instructions both accomodate an immediate value to be specified. What is the maximum number of bits that can be specified for each instruction format?
- (A) 16 for I, 26 for J
- (B) 20 for I, 26 for J
- (C) 16 for I, 28 for J
- (D) 28 for I, 28 for J
- ANSWER: (A). See Final review: MIPS - Instruction formats for more details.

Which of the following instructions is NOT part of the MIPS instruction set, and is merely a pseudoinstruction that will be converted into real MIPS instructions by the assembler?
- (A) beq
- (B) blt
- (C) sll
- (D) addi
- ANSWER: (B). blt is converted into two instructions: slt and bne.
Which of the following would correctly translate the pseudoinstruction move $t1, $t0 into real MIPS commands?
- (A) add $t1, $t0, $t0
- (B) add $t0, $t1, $t1
- (C) add $t1, $t0, $0
- (D) addi $t0, $t1, 0
- ANSWER: (C). The actual translation would be addi $t1, $t0, 0, which is not listed above. Only (C) would be an accurate translation for every case among the possibilities above.
Which of the following would correctly translate the pseudoinstruction bge $t0, $t1, somelabel into real MIPS commands?
- (A) slt $t2, $t1, $t0; beq $t2, $0, somelabel
- (B) slt $t2, $t0, $t1; beq $t2, $t0, somelabel
- (C) slt $t2, $t1, $t0; bne $t2, $0, somelabel
- (D) slt $t2, $t0, $t1, bne $t2, $t0, somelabel
- ANSWER: (C). The actual translation would make use of register \$1, not \$t2.
When we use the pseudoinstruction li to load a register with an immediate, the assembler actually translates this into two instructions, because the register is able to hold a 32-bit value but only a 16-bit immediate can be specified per MIPS instruction. The first of these two instructions is lui (load upper immediate), which takes the upper 16 bits provided and stores them as the upper 16 bits of the register. What is the other command?
- (A) ori
- (B) addi
- (C) add
- (D) and
- ANSWER: (A). See Final review: MIPS - Storing an immediate 32-bit value for more details.

What would be stored in \$s0 and \$s1 after the execution of the following instructions?
```
li $t0, -50000
li $t1, 50000
slt $s0, $t0, $t1
sltu $s1, $t0, $t1
```
- (A) 0 in \$s0 and 0 in \$s1
- (B) 0 in \$s0 and 1 in \$s1
- (C) 1 in \$s0 and 0 in \$s1
- (D) 1 in \$s0 and 1 in \$s1
- ANSWER: (C).
What would be stored in \$s0 and \$s1 after the execution of the following instructions? (Same type of question as the previous one, but with different numeric values.)
```
li $t0, -50000
li $t1, 50001
slt $s0, $t0, $t1
sltu $s1, $t0, $t1
```
- (A) 0 in \$s0 and 0 in \$s1
- (B) 0 in \$s0 and 1 in \$s1
- (C) 1 in \$s0 and 0 in \$s1
- (D) 1 in \$s0 and 1 in \$s1
- ANSWER: (C). For sltu, recall that -50000 is stored in two's complement form, and since its MSB is 1 it will definitely not be seen as less than 50001.

Let's say you're a child function and you were called by a parent who had put values in all of the following registers. Which register should the parent function NOT expect to be unchanged once execution goes back to the parent? In other words, which registers are you allowed to freely change, by MIPS conventions?
- (A) $sp
- (B) $s0
- (C) $s1
- (D) $ra
- ANSWER: (D). Although you can change $sp, you cannot freely change it in that by the time you return the flow of execution to the parent, $sp should be the same as it was before. How else can the parent function retrieve things it has placed on the stack? At least that's my interpretation of it. (In any case, it definitely should not expect whatever is in $ra to be saved, especially if the child function was called with jal.)

Which of the following best describes the sizes of the various parts of MIPS memory?
- (A) The kernel and user regions are both divided into "data" and "instruction" subregions, but the kernel region is much smaller than the user region.
- (B) The user region is divided into "data" and "instruction" subregions, while the kernel region is not divided into subregions.
- (C) The kernel and user regions are of the same size, and each is divided into "data" and "instruction" subregions, with the "data" subregion being much larger than the "instruction" subregion.
- (D) The kernel and user regions are of the same size, and each is divided into "data" and "instruction" subregions, with the "instruction" subregion being much larger than the "data" subregion.
- ANSWER: (C). See Final review: MIPS - Memory for more details.

Which of the following operations would change the contents of \$t0 from 0x0000000f into 0x0000003c
- (A) sll $t0, 2
- (B) srl $t0, 2
- (C) sll $t0, 4
- (D) srl $t0, 4
- ANSWER: (A). See Final review: MIPS - Bitshift operations for more details.

Let's say we have an array with 4 integer elements. The address of the first element in the array is stored in \$t0. Which of the following gives us the result of the last element of the array (stored in \$t1)?
- (A) addi $t1, $t0, 3; sll $t1, 2;
- (B) addi $t1, $t0, 16
- (C) sll $t0, 2; addi $t1, $t0, 3
- (D) addi $t1, $t0, 12
- ANSWER: (D). See Final review: MIPS - Array operations for more details.

How many bits does the string hello world! take up?
- (A) 12
- (B) 48
- (C) 104
- (D) 384
- ANSWER: (C). Each character is a byte, which is 8 bits, and there are 12 characters + 1 null terminator, and $13 \times 8 = 104$.
Which of the following statements about working with strings in MIPS is incorrect?
- (A) To load individual characters from memory or write them back into memory, we use the instructions lc and sc, respectively.
- (B) When loading a character from memory, the numerical value is sign-extended to fill all 32 bits of the register.
- (C) When saving a character into memory, the upper 24 bits in the register are ignored.
- (D) We can compute the length of a string by making the use of the fact that the null terminator for strings is \$0.
- ANSWER: (A). The commands are lb and sb.

Which of the following statements is incorrect?
- (A) To align subsequent declarations with word boundaries, we can use the directive .align 2.
- (B) Static data must be declared under the .data section (not underneath the .text section).
- (C) To allocate enough space for exactly 100 bits, we can use the directive .space 100
- (D) To declare a string containing a line break, we can use the directive .asciiz "\n"
- ANSWER: (C). .space 100 would allocate space for 100 bytes, not bits.

Which of the following statements about system calls is incorrect?
- (A) To exit the program, we store 10 in \$v0.
- (B) To print an integer, we store 1 in \$v0, and place the integer itself in \$v1.
- (C) After reading an integer from the command prompt, the integer itself is stored in \$v0.
- (D) To print a string, we must have created the string beforehand, either in the static data section or dynamically.
- ANSWER: (B). The integer is stored in \$a0, the first argument register.

The following commands were used to store the contents of registers \$s0 and \$s1 onto the stack:
```
addi $sp, $sp, -8
sw $s0, 0($sp)
sw $s1, 4($sp)
# insert various unrelated instructions here
```
Assuming that neither the stack pointer nor the stack has been changed during the "various unrelated instructions" part, which of the following would allow you to recover the contents of \$s0 and \$s1 while returning \$sp to its original (pre-decremented) value?
- (A) addi $sp, $sp, 8; lw $s0, 4($sp); lw $s1, 0($sp)
- (B) addi $sp, $sp, 8; lw $s0, 0($sp); lw $s1, 4($sp)
- (C) lw $s0, 4($sp); lw $s1, 0($sp); addi $sp, $sp, 8
- (D) lw $s0, 0($sp); lw $s1, 4($sp); addi $sp, $sp, 8
- ANSWER: (D). See Final review: MIPS - Using the stack for more details.

Which of the following statements about multiplication and division is incorrect?
- (A) Integer multiplications takes an input two 32-bit values and returns a 64-bit value
- (B) The result of a multiplication is stored in a read-only (for the programmer at least) "product" register
- (C) The product of two numbers is accesssed using two separate instructions - mfhi to get bits 0-31 (the rightmost bits), and mflo to get bits 32-63
- (D) The div command stores the quotient and the remainder in the product register, and the two can be accessed using mfhi and mflo
- ANSWER: (C). See Final review: MIPS - Multiplication and division for more details.

Which of the following statements about floating point operations is true?
- (A) Floating point operations are done in the ALU, just as with integers.
- (B) If all the floating point registers are full, we can store 32 different double-precision floats.
- (C) When using instructions that require a double-precision float, only the first register (the even register) needs to be mentioned.
- (D) \$f0 is hardwired to the value 0.0.
- ANSWER: (C). (A) is false because a different coprocessor is needed, (B) is false because there are 32 registers and so we can only store 16 double-precision floats, and (D) is sadly not true either.

Let the register $t0 hold the value 14925, and let the registers $f0 and $f1 hold the value 19485.105 (double precision). We want to compute the sum of the two numbers (with as much precision as possible) and store it in $f10. How could we go about doing this?
- (A) mtc1 $t0, $f2; cvt.d.w. $f2, $f2; add.d $f4, $f0, $f2
- (B) mfc1 $t0, $f1; cvt.s.w $f1, $f1; add.s $f10, $f0, $f1
- (C) mtc1 $t0, $f2; cvt.w.d $f2, $f0; add $f10, $f0, $f1; add $f10, $f10, $f2
- (D) cvt.s.w $t0, $t0; mfc1 $f2, $t0; add.s $f10, $f2, $f0
- ANSWER: (A). None of the others make sense.

Which of the following statements about exception handling is true?
- (A) Exception handling is done within coprocessor 1.
- (B) The return address (the line that immediately follows the one that caused the exception) is stored in a kernel-only register, called EPC.
- (C) Trying to access an illegal address will not cause an exception, but it will probably cause errors in your program
- (D) Trying to divide 1.0 by 0.0 in the FPU will result in an exception
- ANSWER: (B). (A) is false because exception handling is done by coprocessor 0, (C) is false because it will cause an exception, and (D) is false because division by zero (and also overflow errors) result in something like $\pm \infty$ or NaN for floats.

Which of the following instructions could this single-cycle datapath description be referring to?

Two source registers (ReadReg) and one destination register (WriteReg) are selected, and the values are read from the source registers and sent as input to the ALU. The ALU operation is performed, the result is written to the destination register, and the PC is updated.
- (A) add
- (B) ori
- (C) li
- (D) sll
- ANSWER: (A). No immediate is used, so (B) and (C) are out (both are I-format). The shamt is not used, so (D) is out.
(Same type of question)

Two source registers (ReadReg) are selected, and their values are read. One of these values is sent along with an immediate value to the ALU. The value in the other source register is then written into memory, at the address specified by the output of the ALU. The PC is then updated.
- (A) lui
- (B) lw
- (C) sw
- (D) slt
- ANSWER: (C). The description of sw is fairly unique (although it would work for sb too I suppose).
(Same type of question)

Two source registers (ReadReg) are selected, and their values are read and sent to the ALU. An immediate value is also sent to the ALU, along with the value of the PC (program counter). Depending on the output of the first ALU operation, either the output of the ALU or PC + 4 is selected and written back to the ALU.
- (A) lb
- (B) j
- (C) jal
- (D) beq
- ANSWER: (D). I figured that the datapaths for bne and beq (former is given in the lecture notes - see Final review: MIPS - Single-cycle datapaths) should be similar, so I tried to describe the datapath for it as accurately as I could. This description can definitely be improved, though.

Later

Later

Which of the following commands would NOT result in the register $t0 being set to 0?
- (A) li $t0, 0
- (B) xor $t0, $t0, $t0
- (C) and $t0, $t0, $0
- (D) ori $t0, $t0, 0
- ANSWER: (D). Fairly straightforward. Inspired by a stackoverflow question.

given some simple instructions, write down the output or draw the datapath
- examples:
  - li \$t1, 100
  - addi \$t2, \$t1, -40
  - swapping two words/bytes or whatever (trace out the steps)
- write down the contents of \$t2 and \$t1 at the end
- with casting, adding ints/floats in the CPU or in the FPU, then compare etc
given some instructions that may cause data hazards, give solutions for dealing with them etc

MIPS sample questions

1MIPS: the basics¶

1.1Instruction formats¶

1.2Pseudoinstructions¶

1.3Signed vs unsigned instructions¶

1.4Register conventions¶

1.5Memory¶

2Various MIPS operations¶

2.1Bitshift operations¶

2.2Array operations¶

2.3Working with strings¶

2.4Assembler directives¶

2.5IO and system calls¶

2.6Using the stack¶

2.7Multiplication and division¶

2.8Floating point operations¶

2.9Type conversion¶

2.10Exception handling¶

3Datapaths¶

3.1Single-cycle datapaths¶

3.2Multi-cycle datapaths¶

3.2.1Microinstructions¶

3.2.2Pipelining¶

4Miscellaneous¶

5Notes to self¶